RISC-V - The Bare Minimum
Updated 2019-09-10
RISC-V is an instruction set architecture (ISA). It started as a non-proprietary open-source ISA.
ISA
What is an ISA? It is a contract between the software and hardware such that they interface with each other.
note to the slide diagram (load-store architecture)
- The instruction flow is a stream of instructions from the compiled program like an assembly line.
Ultimately the choice of ISA does not matter in terms of performance.
Making a new ISA is hard because:
- need people to build all the infrastructure such as compilers
- compete with existing ISAs
Registers
There are 32 general purpose registers for operation in RISC-V (x0-x31). There are also 32 floating point extension registers (f0-f31).
Instructions
More about RISC-V specifications can be found in Appendix-A of the textbook.
Arithmetic Instructions
Load-Store Instructions
These are the “supply” and “release” instructions of the ISA. Without load-store instructions arithmetic is useless as it cannot load or store input and output.
insert table
Control Flow Instructions
Programs all have logic, which require control-flow instructions. The control flow instructions observes some input condition, and execute a branch/jump to somewhere else in the program.