Asynchronous Datapath

• Concepts
  • Four Phase Handshaking
  • Two-Phase Handshaking
  • Encoding Scheme
    • Bundled Data (Single Rail)
    • Dual rail
    • Two Phase Dual Rail
• Implementation
  • Muller pipeline
  • Micropipeline
• GALS

Concepts

Recall how we traditionally build synchronous datapath (page 4), we have FFs that goes into combinational logic that goes into more FFs etc.

What is different in asynchronous designs? One is that we don’t have clock, and thus no FFs.

First we change the FFs to latches. The latches are level sensitive instead of edge sensitive. Instead of a clock, we use some protocol to ensure that everything is working together. The protocol is a form of handshake.

An example of a handshake is ready/acknowledge protocol.

page 6

Four Phase Handshaking

AKA return to zero

For one transaction:

1. Sender issues data and sets ready to high.
2. Receiver reads data and sets acknowledge to high.
3. Sender accepts acknowledge signal and sets ready to low, and data is no longer valid.
4. Receiver sets acknowledge to low.

page 8

Advantages and Disadvantages

• Needs two round trips between each transaction
• Has evaluate phase (pos-edge ready and ack) and reset phase (neg-edge of ready and ack)
• Simpler hardware because control signals always start low

Two-Phase Handshaking

AKA non-return to zero / transitional signaling.

For one transaction:

1. Sender issues data and toggles ready signal
2. Receiver reads data and toggles acknowledge signal

page 9

Advantages and Disadvantages

• Faster and uses lower power
• More complex hardware because of the transition-based signaling instead of level based. Thus some state machine is required.

Encoding Scheme

Bundled Data (Single Rail)

No special encoding, one wire is used for each bit of data. For each stage we only need one ready and ack control signal for all data bits.

page 12

Problem: how do we know that each data bit wire is ready in order for the ready signal to be asserted. The sender could not even know when the data will ready.

More specifically, we want the data lines to be faster than the control signals ready and ack. So we need to put delay (using inverter buffers) to delay the control signals. How many inverters to add depends on the critical path timing. The timing analysis is difficult to do because the tool needs to be really conservative.

Dual rail

page 14

The solution is using dual rail. Each bit of data is encoded using two wires. The ready status is encoded INTO the data.

Consider the example one page 15, we are transmitting 1 bit using two wires; A0 and A1. By using two wires, we encoded a new empty state (00) in which the receiver will do nothing. Because of the empty state, the Hamming distance is within 1.

The transaction only required one transition.

At the start, the data is (00) to denote empty (no data).

1. Sender sets data wire pair to (10) or (01) which corresponds to 1 or 0 for the data
2. Receiver sees non-empty data, reads it and sets ack signal to high. Thus, the ‘ready’ signal is built in into the data lines
3. Sender accepts ack and sets data wire pair to empty state again (00)
4. Receiver de-asserts ack to low

Two Phase Dual Rail

• Two wires to encode each bit of data
• In 2-phase handshaking, use transitions to represent values instead of level. Thus, we don’t have an empty state.

Implementation

Muller pipeline

page 27

Recall Muller: the hysteresis protection (refer back to previous slide set / notes).

Micropipeline

GALS

Globally asynchronous locally synchronous