Asynchronous Logic
Updated 2018-03-26
- Asynchronous FSM
- Design
- Fundamental Difference
- Asynchronous Stability
- Glitches
- State Encoding Assignment
What if we take out the clock? The clock synchronize all the signals, this makes digital logic easy. Why would we want to do this?
- In synchronous design, clock period is dictated by the longest path
- Instantaneous power is a problem because everything is synchronized
- Excessive noise at the frequency of the clock
- In large chips, clock distribution is difficult
Asynchronous FSM
Consider page 6 asynchronous finite state machine, rather than having the transition timing based on the clock edge, the transition occurs as soon as possible.
In fact, inside the flip flops are just combinational feedback with asynchronous logic.
Combinational Loop
Two inverters fed into each other is combinational loop and can be used for storage (page 8). Adding external signals that over powers the signal makes the inverters essential NOR gates. Thus we get an SR latch. (SRAM is built this way). The SR latch is a state machine.
The state transition table can be made:
| S | R | Q_next |
|---|---|---|
| 0 | 0 | Q |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | :( |
page 13 state bubble diagram
When does Q takes the value of next Q?
This happens almost instantly whenever S is set.
Design
- Start with state diagram
- assigne ncodring to states
- state transition table
- Kmap from table
- boolena equations for next state
Two concerns:
- Glitches
- state encoding
We are not used to these problems because they don’t exist in synchronous designs.
Example: Muller C Experiment
page 17
Here is the truth table:
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | Y |
| 1 | 0 | Y |
| 1 | 1 | 1 |
State assignmnet
we have two states, so we just use 1 bit. Let state 0 be 0 and let state 1 be 1. The transition table is page 19
WIP ;_;
Fundamental Difference
Asynchronous FSM immediately changes state. There will be glitches but as long as we sample it at the right time, we are good. Another way of thinking is is that there is an imaginary clock with its frequency determined by the propagation delay.
Asynchronous Stability
Consider the Muller C Experiment implementation again, it is stable if the input causes the state to fix on it self. The circuit is unstable if Q_next=!Q.
page 27
Glitches
Due to glitches, the system might be transitioned into undesired states. Thus, the golden rule is: next state and output logic must be glitch free.
Recall the the glitch is just a temporary spike in the output signals. A hazard is a possibility of glitching due to circuit structure. Static hazard occurs when the potential for glitching to occur when the signal values should not change (transitions when there isn’t suppose to be any). Dynamic hazard are potential for glitching to occur when the signal value should be changed, but multiple transitions are observed.
Static Glitch
page 31
The solution is to mask the glitch.
State Encoding Assignment
Between any two adjacent states, the change is only 1 bit. In other words, the Hamming Distance / Manhattan distance in binary must be only 1. This is so that only one bit changes at one time.
If more than 1 bit is trying to change at one time, then there exists a race condition. Which bit will change first? This can lead to glitches as we don’t have a clock to synchronize timing.